This invention relates to programmable logic array integrated circuit devices, and more particularly to the provision of relatively large blocks of random access memory ("RAM") on such devices.
Commonly assigned, co-pending, Cliff et al. U.S. patent applications Ser. No. 08/245,509, filed May 18, 1994, and Ser. No. 08/442,795, filed May 17, 1995, show programmable logic array integrated circuit devices with relatively large blocks of random access memory ("RAM") in addition to the usual large number of programmable logic modules and the usual programmable network of interconnection conductors. (These two patent applications are hereby incorporated by reference herein.) These RAM blocks can be programmed at the same time that the rest of the device is programmed and thereafter used as read-only memory ("ROM") to perform logic, arithmetic functions, state machine operations, etc., that may be more efficiently performed in one large memory block (or a small number of such blocks) rather than in several of the individually relatively small logic modules. Alternatively, the RAM blocks may be used as random access memory during use of the device to perform logic.
From the foregoing it will be seen that the above-mentioned RAM blocks have several possible uses and require several different modes of operation. They should be programmable like other memory cells on the device (i.e., the other memory cells that control the functioning of the logic modules and the interconnection conductor network). This is necessary when the RAM blocks are to be used as ROM. Their programming in this way should be capable of verification like other memory cells on the device (i.e., reading out of the programmed data to ensure that the memory cells are programming properly). The RAM blocks should also be programmable as random access memory during use of the device to perform logic. And the RAM blocks should be readable as random access memory or read-only memory, also during use of the device to perform logic. All of these possible uses and modes of operation of these RAM blocks tend to significantly complicate the circuitry required to provide such blocks.
In view of the foregoing, it is an object of this invention to improve and simplify the provision of blocks of RAM on programmable logic array integrated circuit devices.
It is a more particular object of this invention to provide RAM block circuitry for use on programmable logic array integrated circuit devices that facilitates programming and verification of the RAM block for use as ROM, and that also facilitates programming and reading the block as RAM during use of the device to perform logic.